1. Field
Exemplary embodiments of the present invention relate to a semiconductor device for a multi-test mode and a testing method thereof.
2. Description of the Related Art
As the integration of semiconductor devices such as memory devices (DRAM and flash memory) increases, more time and costs incur in testing the semiconductor devices. Particularly, a test for deciding the presence of defective memory cells takes a considerable time.
In a general testing operation of a defective cell, an activating operation of cell blocks, a read (or write) operation and a pre-charging operation are sequentially performed. Here, the cell block includes at least one word line. First, one of a plurality of cell blocks is activated by decoding an inputted address ADD<0:M>. Specifically, one of word lines constituting the activated cell block is activated. A read or write operation is performed on a cell block activated in response to a read or write command. Subsequently, a pre-charging operation is performed. The operations described above are repeatedly performed on all the word lines constituting the activated cell block.
A multi-test method for testing the presence of defect of a memory cell by activating a plurality of cell blocks is used to reduce a test time of defective cells. In the multi-test method, an active operation and a pre-charge operation can be simultaneously performed on the plurality of cell blocks, so that the overall test time can be reduced.
Meanwhile, in order to increase a yield of memory cells, when a defect occurs in a memory cell of a general semiconductor device, a cell block including the defective cell is replaced with a redundancy cell block separately provided in the memory device. After a specific cell block is repaired, an inputted address indicating the specific cell block and a stored repair address indicating the repaired cell block are compared through a decision circuit. If both the addresses are identical to each other, the cell block indicated by the inputted address is decided as a defective cell block. Subsequently, the redundancy cell block is activated in place of the cell block indicated by the inputted address, and a read (or write) operation is performed on the activated cell block. On the contrary, if the inputted address is different from the stored repair address, the cell block indicated by the inputted address is decided as a normal cell block, and a read (or write) operation is performed on the cell block indicated by the inputted address.
In a multi-test mode, at least two cell blocks of N cell blocks are simultaneously activated. However, since a plurality of cell blocks are simultaneously activated in the multi-test mode, a plurality of signals respectively indicating the plurality of cell blocks are simultaneously inputted to a decision circuit and cause an inaccurate decision operation.